Non-volatile Memory System Using Strap Cells In Source Line Pull Down Circuits

ABSTRACT

The present invention relates to a flash memory device that uses strap cells in a memory array of non-volatile memory cells as source line pull down circuits. In one embodiment, the strap cells are erase gate strap cells. In another embodiment, the strap cells are source line strap cells. In another embodiment, the strap cells are control gate strap cells. In another embodiment, the strap cells are word line strap cells.

RELATED APPLICATION

This application claims the benefit of Chinese Patent Application No.202010304167.2, filed Apr. 17, 2020.

TECHNICAL FIELD

The present invention relates to a non-volatile memory device thatutilizes existing strap cells in the array in source line pull downcircuits.

BACKGROUND OF THE INVENTION

Non-volatile memory cells are well known in the art. Examples ofnon-volatile memory cells known in the prior art are shown in FIGS. 1-6.

FIG. 1 depicts stacked-gate non-volatile memory cell 110. Each memorycell 110 includes source region (also referred to as source lineterminal) 14 and drain region 16 formed in semiconductor substrate 12,with channel region 18 there between. Floating gate 20 is formed overand insulated from (and controls the conductivity of) channel region 18,and over a portion of each of the drain region 16 and the source region14. Control gate terminal 22 (which here is coupled to a word line) isdisposed over and insulated from floating gate 20. The floating gate 20and control gate terminal 22 are insulated from each other and from thesubstrate 12 by a gate oxide. Bitline terminal 24 is coupled to drainregion 16.

Programming is performed using hot electron injection from channel 18 tofloating gate 20 in the channel region next to the drain region 16.

Erasing is performed using by Fowler-Nordheim electron tunneling fromfloating gate 20 to substrate 12.

Reading is performed by placing positive read voltages on the drainregion 16 and control gate terminal 22 (which turns on channel region18). If the floating gate 20 is positively charged (i.e. erased ofelectrons), then channel region 18 under the floating gate 20 is turnedon as well, and current will flow across the channel region 18, which issensed as the erased or “1” state. If the floating gate 20 is negativelycharged (i.e. programmed with electrons), then the channel region underthe floating gate 20 is mostly or entirely turned off, and current willnot flow (or there will be little flow) across the channel region 18,which is sensed as the programmed or “0” state.

Table No. 1 depicts typical voltage ranges that can be applied to theterminals of memory cell 110 and substrate 12 for performing read,erase, and program operations:

TABLE NO. 1 Operation of Stacked-Gate Non-Volatile Memory Cell 110 ofFIG. 1 CG BL SL Substrate Read 1 0-5 V 0.1-2 V 0-2 V 0 V Read 2 0.5-2 V0-2 V 2-0.1 V 0 V Erase −8 to −10 V/0 V FLT FLT 8-10 V/15-20 V Program8-12 V 3-5 V/0 V 0 V/3-5 V 0 V

“Read 1” is a read mode in which the cell current is output on the bitline. “Read 2” is a read mode in which the cell current is output onsource line terminal 14. In the program mode, the bit line terminal isset to VDD (typically 3-5 V) and the source line terminal is set to 0 Vto inhibit programming of the cell, and the bit line terminal is set to0 V and the source line terminal is set to VDD (typically 3-5 V) toprogram the cell.

FIG. 2 depicts split-gate non-volatile memory cell 210. Each memory cell210 includes source region (source line terminal) 14 and drain region 16formed in semiconductor substrate 12, with channel region 18 therebetween. Floating gate 20 is formed over and insulated from (andcontrols the conductivity of) a first portion of the channel region 18,and over a portion of the source region 14. Word line terminal 22 (whichis typically coupled to a word line) has a first portion that isdisposed over and insulated from (and controls the conductivity of) asecond portion of the channel region 18, and a second portion thatextends up and over the floating gate 20. The floating gate 20 and wordline terminal 22 are insulated from the substrate 12 by a gate oxide.Bitline terminal 24 is coupled to drain region 16.

Memory cell 210 is erased (where electrons are removed from the floatinggate) by placing a high positive voltage on the word line terminal 22,which causes electrons on the floating gate 20 to tunnel through theintermediate insulation from the floating gate 20 to the word lineterminal 22 via Fowler-Nordheim tunneling.

Memory cell 210 is programmed (where electrons are placed on thefloating gate) by placing a positive voltage on the word line terminal22, and a positive voltage on the source region 14. Electron currentwill flow from the drain region 16 towards the source region 14 (sourceline terminal). The electrons will accelerate and become energized(heated) when they reach the gap between the word line terminal 22 andthe floating gate 20. Some of the heated electrons will be injectedthrough the gate oxide onto the floating gate 20 due to the attractiveelectrostatic force from the floating gate 20.

Memory cell 210 is read by placing positive read voltages on the drainregion 16 and word line terminal 22 (which turns on the portion of thechannel region 18 under the word line terminal). If the floating gate 20is positively charged (i.e. erased of electrons), then the portion ofthe channel region 18 under the floating gate 20 is turned on as well,and current will flow across the channel region 18, which is sensed asthe erased or “1” state. If the floating gate 20 is negatively charged(i.e. programmed with electrons), then the portion of the channel regionunder the floating gate 20 is mostly or entirely turned off, and currentwill not flow (or there will be little flow) across the channel region18, which is sensed as the programmed or “0” state.

Table No. 2 depicts typical voltage ranges that can be applied to theterminals of memory cell 210 for performing read, erase, and programoperations:

TABLE NO. 2 Operation of Non-Volatile Memory Cell 210 of FIG. 2 WL BL SLRead 1 0.5-3 V 0.1-2 V 0 V Read 2 0.5-3 V 0-2 V 2-0.1 V Erase ~11-13 V 0V 0 V Program 1-2 V 1-3 μA 9-10 V

“Read 1” is a read mode in which the cell current is output on the bitline. “Read 2” is a read mode in which the cell current is output onsource line terminal 14.

FIG. 3 depicts split-gate non-volatile memory cell 310. Memory cell 310is similar to memory cell 210 of FIG. 2 with the addition of controlgate (CG) terminal 28. Control gate terminal 28 is biased at a highpositive voltage, e.g., 10V, in programming, low or negative voltage inerase, e.g., 0 v/−8V, low or mid-range voltage in read, e.g., 0 v/2.5V.Other terminals are biased similarly to that of FIG. 2.

FIG. 4 depicts split-gate non-volatile memory cell 410. Memory cell 410comprises source region (source line terminal) 14, drain region 16,floating gate 20 over a first portion of channel region 18, a selectgate 22 (typically coupled to a word line, WL) over a second portion ofthe channel region 18, a control gate 28 over the floating gate 20, andan erase gate 30 over the source region 14. Here, all gates arenon-floating gates except floating gate 20, meaning that they areelectrically connected or connectable to a voltage source. Programmingis performed by heated electrons from the channel region 18 injectingthemselves onto the floating gate 20. Erasing is performed by electronstunneling from the floating gate 20 to the erase gate 30.

Table No. 3 depicts typical voltage ranges that can be applied to theterminals of memory cell 410 for performing read, erase, and programoperations:

TABLE NO. 3 Operation of Non-Volatile Memory Cell 410 of FIG. 4 WL/SG BLCG EG SL Read 1 0.5-2 V 0.1-2 V 0-2.6 V 0-2.6 V 0 V Read 2 0.5-2 V 0-2 V0-2.6 V 0-2.6 V 2-0.1 V Erase −0.5 V/0 V 0 V 0 V/−8 V 8-12 V 0 V Program1 V 1 μA 8-11 V 4.5-9 V 4.5-5 V

“Read 1” is a read mode in which the cell current is output on the bitline. “Read 2” is a read mode in which the cell current is output on thesource line terminal.

FIG. 5 depicts split-gate non-volatile memory cell 510. Memory cell 510is similar to memory cell 410 of FIG. 4 except that memory cell 510 doesnot contain an erase gate EG terminal. Programming is performed byheated electrons from the channel region 18 injecting themselves ontothe floating gate 20. An erase is performed by biasing the substrate 12to a high voltage and biasing the control gate CG terminal 28 to a lowor negative voltage such that electrons tunnel from the floating gate 20to the channel region 18. Alternatively, an erase is performed bybiasing word line terminal 22 to a positive voltage and biasing controlgate terminal 28 to a negative voltage such that electrons tunnel fromthe floating gate 20 to the word line terminal 22. Programming andreading is similar to that of FIG. 4.

FIG. 6 depicts split-gate non-volatile memory cell 610. Memory cell 610is identical to the memory cell 410 of FIG. 4 except that memory cell610 does not have a separate control gate terminal. The erase operation(whereby erasing occurs through use of the erase gate terminal) and readoperation are similar to that of the FIG. 4 except there is no controlgate bias applied. The programming operation also is done without thecontrol gate bias, and as a result, a higher voltage must be applied onthe source line terminal 14 during a program operation to compensate fora lack of control gate bias.

Table No. 4 depicts typical voltage ranges that can be applied to theterminals of memory cell 610 for performing read, erase, and programoperations:

TABLE NO. 4 Operation of Non-Volatile Memory Cell 610 of FIG. 6 WL/SG BLEG SL Read 1 0.5-2.2 V 0.1-2 V 0-2.6 V 0 V Read 2 0.5-2.2 V 0-2 V 0-2.6V 2-0.1 V Erase −0.5 V/0 V 0 V 11.5 V 0 V Program 1 V 2-3 μA 4.5 V 7-9 V

“Read 1” is a read mode in which the cell current is output on the bitline. “Read 2” is a read mode in which the cell current is output on thesource line terminal.

Memory cells of the types shown in FIGS. 1-6 typically are arranged intorows and columns to form an array. Erase operations are performed onentire rows or pairs of rows at one time, since each word lines controlsa row of memory cells and is coupled to word line terminal 22 of eachcell in that row, and erase gate lines (when present) are shared bypairs of rows of memory cells and are coupled to erase gate terminals 30of each cell in those pairs of rows. Source lines typically are coupledto source line terminals 14 of one row of memory cells or two adjacentrows of memory cells. Bitlines typically are coupled to bit lineterminals 24 of one column of memory cells 24.

For each of the prior art memory cells of FIGS. 1-6, and as can be seenin the above Tables, it often is necessary to pull the source line downto ground, i.e. to 0 volts, and to do so relatively quickly.

FIG. 7 depicts a typical prior art technique for doing this. Memorysystem 700 comprises memory cell 710, word line 722, control gate line726, erase gate line 728, bit line 720, and source line 714. Memory cell710 can be any of the types shown in FIGS. 1-6, namely, memory cell 110,memory cell 210, memory cell 310, memory cell 410, memory cell 510,memory cell 610, or another type of memory cell. Source line 714 iscoupled to pull down transistor 730, which here comprises a single NMOStransistor. When the gate of pull down transistor 730 is activated,source line 714 is pulled down to ground. In a flash memory system,numerous pull down circuits will be required, and each source line 714may require more than one pull down circuit depending on the capacitanceof the source line 714. The pull down transistors 714 require operatingvoltages of around 0-1.2 V for low voltage operations and 4-5-11.5 V forhigh voltage operations, as shown in Tables 1-4. This means that pulldown transistor 730 needs one or both of a high voltage transistor type(e.g., 11.5V transistor) or an IO transistor type (e.g., 2.5V or 3Vtransistor), which takes up die space and increases the overall cost andcomplexity of the system. In the situation where both types are present,they typically will be connected to ground on one end and to amultiplexor on the other end, where the multiplexor connects one of thetransistors to the source line in response to a control signal. Inaddition, the pull down transistors can incur overstress and breakdownwhen memory cell 710 is programmed.

Applicant presented an improvement over memory system 700 in PCTPublication No. WO 2017/044251 A1, titled “Flash Memory System UsingDummy Memory Cell As Source Line Pull Down Circuit,” which isincorporated herein by reference. This memory system is depicted inFIGS. 8 and 9.

With reference to FIG. 8, flash memory system 800 comprises exemplarymemory cell 710 and exemplary dummy memory cell 810. Dummy memory cell810 is of the same construction as memory cell 710 except that dummymemory cell 810 is not used to store data. Source line 714 of memorycell 710 is coupled to source line 814 of dummy memory cell 810, aswould typically be the case if memory cell 710 and dummy memory cell 810are in the same row within an array. Word line 722 is coupled to wordline 822, and bit line 720 is shared among memory cells 800 of thecolumn.

In the example shown, memory cell 710 and dummy memory cell 810 followthe design of memory cell 410 in FIG. 4. It will be understood thatmemory cell 710 and dummy memory cell 810 also can follow the design ofmemory cell 310 in FIG. 3 or memory cell 510 in FIG. 5 (in which caseerase gates 728 and 828 will not be present), of memory cell 610 in FIG.6 (in which case control gates 726 and 826 will not be present), or ofmemory cell 110 in FIG. 1 or memory cell 210 in FIG. 2 (in which caseerase gates 728 and 828 and control gate 726 and 826 will not bepresent).

When memory cell 710 is in read mode or erase mode, source line 814 iscoupled to ground through the dummy memory cell 810 and dummy bitline820, which is switchably coupled to ground, which results in source line714 and source line 814, anything else that is electrically connected tobit line 820, being pulled to ground. Dummy memory cells 810 arerequired to be erased before a read operation.

When the memory cell 710 is in program mode, dummy bitline 820 isswitchably coupled to an inhibit voltage such as VDD. This will placedummy memory cell 810 in a program inhibit mode which maintains dummymemory cell 810 in an erased state. There can be a plurality of dummymemory cells 810 for each memory cell 710 to strengthen the pull down ofthe source line 714 to ground.

FIG. 9 depicts flash memory system 900, which comprises exemplary memorycells 920 and exemplary dummy memory cell circuit 910. Dummy memory cellcircuit 910 comprises a plurality of dummy memory cells coupled to oneanother. In this example, source line 930 (also labeled SL0) and sourceline 940 (also labeled SL1) from memory cells 920 are coupled to sourceline terminals of dummy memory cell circuit 910. In this example, sourceline 930 SL0 and source line 940 SL1 are connected together.

Thus, the source lines for an entire sector or sectors of memory cells920 can be coupled together to a source line of dummy memory cellcircuit 910 comprising dummy memory cells from the same rows of cellsthat are part of the sector or sectors.

When memory cells 920 are in read mode or erase mode, dummy memory cellcircuit 910 will be coupled to ground through the dummy bitlines. Thedummy memory cells are required to be erased before a read operation.The erased dummy memory cells, when coupled to ground through the dummybitlines will pull source lines 930 and 940 to ground.

When memory cells 920 are in program mode, the dummy bitlines of dummymemory cell circuit 910 will be coupled to an inhibit voltage such asVDD. This will place the dummy memory cells of dummy memory cell circuit910 in a program inhibit mode, which maintains the dummy memory cells inan erased state.

Optionally, word line 950 (also labeled WL_rdcellpdwn, which is separatefrom wordlines of the memory cell 920) and control gate 960 (alsolabeled CG_rdcellpdwn, which is separate from control gates of thememory cell 920) are biased at a different voltage than that of thememory cell 920, such as VDD or higher, during read or standby modes tominimize the current drop across the dummy memory cells of dummy memorycell circuit 910.

The systems of FIGS. 8 and 9 have numerous benefits over the prior artsystem of FIG. 7. First, the source line pull down current isdistributed among many dummy memory cells and metal paths, which resultsin lower electromagnetic interference and less decoding interconnection.Second, there is less power dissipation across the dummy memory cellscompared to the pull down high voltage transistors of the prior art.Third, the embodiments require less die space versus the high voltagetransistor pull down solution. Fourth, bias and logic control of theembodiments are simpler than that of the pull down transistors of theprior art. This results in less overstress and breakdown duringprogramming modes.

However, the embodiments of FIGS. 8 and 9 require additional die spacefor the dummy memory cells of the dummy memory cell circuit. Thisincreases the size, complexity, and manufacturing cost of the die.

Prior art memory systems also contain strap cells. FIGS. 10A, 10B, 10C,and 10D depict prior art memory systems 1000-1, 1000-2, 1000-3, and1000-4, respectively, which comprise exemplary memory cell 1010 andexemplary strap cell 1020, i.e. exemplary strap cell 1020-1, 1020-2,1020-3 and 1020-4, respectively. Strap cell 1020 is part of a strap rowor a strap column that typically is present in the array as an area inwhich physically connections can be made between one or more of erasegate lines, source lines, control gate lines, and word lines and anotherstructure outside of the array (such as a driver, low voltage decoder,or high voltage decoder). Strap cell 1020 contains some, but not alwaysall, of the same components as memory cell 1010.

In each of the examples shown in FIGS. 10A, 10B, 10C, and 10D, memorycell 1010 comprises first bit line terminal 1011, first word lineterminal 1012, first control gate terminal 1013, first erase gateterminal 1014, and first source line terminal 1015, as would be the caseif memory cell 1010 follows the design of memory cell 410 in FIG. 4.Strap cell 1020 could be one of four different types of strap cells:erase gate strap cell 1020-1 (shown in FIG. 10A), source line strap cell1020-2 (shown in FIG. 10B), control gate strap cell 1020-3 (shown inFIG. 10C), and word line strap cell 1020-4 (shown in FIG. 10D).

1. Erase Gate Strap Cell

With reference to FIG. 10A, strap cell 1020 can be erase gate strap cell1020-1, comprising second bit line terminal 1021, second word lineterminal 1022, second control gate terminal 1023, second erase gateterminal 1024, second source line terminal 1025, and erase gate contact1034, where erase gate contact 1034 connects second erase gate terminal1024 to a structure (such as a low voltage or high voltage decoder)outside of the array containing memory cell 1010 and strap cell 1020-1that drives the erase gate line 1104 connected to second erase gateterminal 1024 as needed during program, erase, and read operations.Second erase gate terminal 1024 is further connected to erase gate line1104 since it is in the same row as memory cell 1010. Memory cell 1010comprises a first word line terminal 1012, a first control gate terminal1013, an first erase gate terminal 1014, a first source line terminal1015 and a first bit line terminal 1011.

FIG. 11A depicts an example of an array containing erase gate strap cell1020-1. Array 1100-1 comprises bit lines 1101, word lines 1102 a and1102 b, control gate lines 1103 a and 1103 b, erase gate line 1104, andsource line 1105. Source line 1105 is located underneath erase gate line1104, and therefore from this view would appear to be the same line eventhough they are separate in the three-dimensional space.

Exemplary memory cell 1010 is depicted. The word line terminal (such asfirst word line terminal 1012 in FIG. 10) of cell 1010 is coupled toword line 1102 a, the control gate terminal of memory cell 1010 (such asfirst control gate terminal 1013 in FIG. 10) is coupled to control gateline 1103 a, the erase gate terminal (such as first erase gate terminal1014 in FIG. 10) of cell 1010 is coupled to erase gate line 1104, andthe source line terminal (such as first source line terminal 1015 inFIG. 10) of memory cell 1010 is coupled to source line 1105.

Bit lines 1101 are coupled to structures outside of array 1100 throughbit line contacts 1106 (which are located at either end of each bitline).

Array 1100 also comprises erase gate strap 1110, which comprisesexemplary erase gate strap cell 1020-1. Erase gate strap 1110 is coupledto erase gate line 1104, since it is in the same row, and thus erasegate line 1104 and erase gate terminal 1014 of memory cell 1010 arecoupled to erase gate contact 1034. Strap cell 1020-1 and erase gatestrap 1110 are not connected to any bit line contacts and therefore arenot connected to its corresponding bit line to a structure outside ofarray 1100. As a result, strap cell 1020-1 and erase gate strap 1110have no pull down function in the prior art.

2. Source Line Strap Cell

With reference to FIG. 10B, strap cell 1020 can be source line strapcell 1020-2. Source line strap cell 1020-2 comprises second bit lineterminal 1021, second word line terminal 1022, second control gateterminal 1023, second source line terminal 1025, and source line contact1035 and does not comprise an erase gate terminal (to provide room forsource line contact 1035), where source line contact 1035 connects to astructure (such as a low voltage or high voltage decoder) outside of thearray containing memory cell 1010 and strap cell 1020-2 that drives thesource line connected to second source line terminal 1025 as neededduring program, erase, and read operations. Memory cell 1010 comprises afirst word line terminal 1012, a first control gate terminal 1013, afirst erase gate terminal 1014, a first source line terminal 1015 and afirst bit line terminal 1011.

FIG. 11B depicts an example of an array containing source line strapcell 1020-2. Array 1100-2-2 is similar to array 1100-1 of FIG. 11A,except that erase gate strap 1110 is replaced with source line strap1120, which comprises exemplary source line strap cell 1020-2.

Source line strap 1120 is coupled to source line 1105, since it is inthe same row, and thus source line 1105 and source line terminal 1015 ofmemory cell 1010 are coupled to source line contact 1035. Source linestrap cell 1020-2 and source line strap 1120 are not connected to anybit line contacts and therefore are not connected via their associatedbit line to a structure outside of array 1100-2. As a result, sourceline strap cell 1020-2 and source line strap 1120 performs no pull downfunction in the prior art.

3. Control Gate Strap Cell

With reference to FIG. 10C, strap cell 1020 can be control gate strapcell 1020-3. Control gate strap cell 1020-3 comprises second bit lineterminal 1021, second word line terminal 1022, second control gateterminal 1023, second source line terminal 1025, control gate contact1033, and source line contact 1035 and does not comprise an erase gateterminal (to provide room for source line contact 1035), where controlgate contact 1033 and source line contact 1035 connect to structures(such as a low voltage or high voltage decoders) outside of the arraycontaining memory cell 1010 and strap cell 1020-3 that drives thecontrol gate line 1103 a and source line 1105 connected to secondcontrol gate terminal 1023 and source line terminal 1025, respectively,as needed during program, erase, and read operations. Memory cell 1010comprises a first word line terminal 1012, a first control gate terminal1013, a first erase gate terminal 1014, a first source line terminal1015 and a first bit line terminal 1011.

FIG. 11C depicts an example of an array containing control gate linestrap cell 1130. Array 1100-3 is similar to array 1100-1 and 1100-2 inFIGS. 11A and 11B, respectively, except that the except that erase gatestrap 1110 or source line strap 1120, respectively, are replaced withcontrol gate line strap 1130, which comprises exemplary control gatestrap cell 1020-3. Control gate line strap 1130, particularly controlgate strap cells 1020-3 (one of which is called out), are respectivelycoupled to control gate lines 1103 a and 1103 b, since they are in thesame row, and thus control gate lines 1103 a, 110 b, and control gateterminals 1013 of memory cells 1010, respectively, are coupled tocontrol gate line contacts 1033 a and 1033 b, respectively. Source line1105 is coupled to second source line terminal 1025, since they are inthe same row, and thus source line 1105 is coupled to source linecontact 1035. Control gate line strap cell 1020-3 and control gate linestrap 1130 are not connected to any bit line contacts and therefore arenot connected via their associated bit line to a structure outside ofarray 1100-3. As a result, control gate line strap cell 1020-3 andcontrol gate line strap 1130 perform no pull down function in the priorart.

4. Word Line Strap Cell

With reference to FIG. 10D, strap cell 1020 can be word line strap cell1020-4. Word line strap cell 1020-4 comprises second bit line terminal1021, second word line terminal 1022, second control gate terminal 1023,second source line terminal 1025, word line contact 1032, and sourceline contact 1035 and does not comprise an erase gate terminal (toprovide room for source line contact 1035), where word line contact 1032and source line contact 1035 connect to structures (such as a lowvoltage or high voltage decoders) outside of the array containing memorycell 1010 and strap cell 1020-4 that drive the word line and source lineconnected to word line contact 1032 and source line contact 1035,respectively, as needed during program, erase, and read operations.Memory cell 1010 comprises a first word line terminal 1012, a firstcontrol gate terminal 1013, a first erase gate terminal 1014, a firstsource line terminal 1015 and a first bit line terminal 1011.

FIG. 11D depicts an example of an array containing word line strap cell1020-4. Array 1100-4 is similar to arrays 1100-1, 1100-2, and 1100-3 ofFIGS. 11A, 11B, and 11C, respectively, except that the except that erasegate strap 1110, source line strap 1120 or control gate line strap 1130,respectively, are replaced with word line strap 1140, which comprisesexemplary word line strap cell 1020-4.

Word line strap 1140, particularly word line strap cells 1020-4 (one ofwhich is called out), are coupled to word lines 1102 a and 1102 b, sincethey are in the same row, respectively, and thus word lines 1102 a and1102 b and word line terminals 1012 of memory cells 1010, are coupled toword line contacts 1032 a and 1032 b, respectively. Source line 1105 iscoupled to second source line terminal 1025, since they are in the samerow, and thus source line 1105 is coupled to source line contact 1035.Strap cell 1020-4 and word line strap 1140 are not connected to any bitline contacts and therefore are not connected via their associated bitline to a structure outside of array 1100-4. Word line strap cell 1020-4and word line strap 1140 therefore perform no pull down function in theprior art.

With reference again to FIGS. 10A-10D and 11A-11D, and as indicatedabove, because memory cell 1010 and strap cell 1020 are located in thesame row, first source line terminal 1015 of memory cell 1010 is coupledto the same source line as second source line terminal 1025 of strapcell 1020, first word line terminal 1012 of memory cell 1010 is coupledto the same word line as second word line terminal 1022 of strap cell1020, first control gate terminal 1013 of memory cell 1010 is coupled tothe same control gate line as second control gate terminal 1023 of strapcell 1020, and first erase gate terminal 1014 of memory cell 1010 iscoupled to the same erase gate line as second erase gate terminal 1024(if present) of strap cell 1020.

In the example shown in FIGS. 10A-10D and 11A-11D, memory cell 1010 andstrap cell 1020 follow the design of memory cell 410 in FIG. 4, with theexceptions described above for strap cells 1020-2, 1020-3, and 1030-4.Memory cell 1010 and strap cell 1020 also can follow the design ofmemory cell 310 in FIG. 3 or memory cell 510 in FIG. 5 (in which casefirst and second erase gate terminals 1014 and 1024 will not bepresent), of memory cell 610 in FIG. 6 (in which case first and secondcontrol gate terminals 1013 and 1023 will not be present), or of memorycell 110 in FIG. 1 or memory cell 210 in FIG. 2 (in which case first andsecond erase gate terminals 1014 and 1024 and first and second controlgate terminals 1013 and 1023 will not be present).

Thus, a strap cell is a cell, not used for storing data, comprising atleast one of an erase gate contact, a control gate contact, a sourceline contact and a word line contact which connect to a structure (suchas a low voltage decoder or high voltage decoder) outside of the arraycontaining the memory cells. The respective erase gate contact, controlgate contact, source line contact and word line contact are verticalcontacts which connect to a metal line, which metal line are connectedto the structure (such as a low voltage decoder or high voltage decoder)outside of the array containing the memory cells.

What is needed is a new technique for pulling source lines to ground ina flash memory system that utilizes less die space than the previousdesign disclosed by Applicant and discussed above with reference toFIGS. 8-9.

SUMMARY OF THE INVENTION

In the embodiments described below, a flash memory device utilizesexisting strap cells in the array in source line pull down circuits.

In one embodiment, a memory system comprises a memory cell comprising afirst bit line terminal and a first source line terminal; a strap cellcomprising a second bit line terminal and a second source line terminal;a source line coupled to the first source line terminal and the secondsource line terminal; and a pull down circuit that selectively couplesthe second bitline terminal to ground when the memory cell is being reador erased and to a voltage source when the memory cell is beingprogrammed.

In certain embodiments, the memory cell comprises a first word lineterminal and the strap cell comprises a second word line terminal. Incertain embodiments, the memory cell comprises a first control gateterminal and the strap cell comprises a second control gate terminal. Incertain embodiments, the memory cell comprises a first erase gateterminal and the strap cell comprises a second erase gate terminal.

In certain embodiments, the strap cell is a source line strap cell,wherein the second source line terminal is connected to a source linecontact. In certain embodiments, the strap cell is a word line strapcell, wherein the second word line terminal is connected to a word linecontact. In certain embodiments, the strap cell is a control gate strapcell, wherein the second control line terminal is connected to a controlgate contact. In certain embodiments, the strap cell is an erase gatestrap cell wherein the second erase gate terminal is connected to anerase gate contact.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a stacked-gate, non-volatile memorycell of the prior art to which the present invention can be applied.

FIG. 2 is a cross-sectional view of a split-gate, non-volatile memorycell of the prior art to which the present invention can be applied.

FIG. 3 is a cross-sectional view of a split-gate, non-volatile memorycell of the prior art to which the present invention can be applied.

FIG. 4 is a cross-sectional view of a split-gate, non-volatile memorycell of the prior art to which the present invention can be applied.

FIG. 5 is a cross-sectional view of a split-gate, non-volatile memorycell of the prior art to which the present invention can be applied.

FIG. 6 is a cross-sectional view of a split-gate, non-volatile memorycell of the prior art to which the present invention can be applied.

FIG. 7 depicts a prior art memory cell with a pull down transistorcoupled to the source line.

FIG. 8 depicts a design previously disclosed by Applicant where a dummymemory cell is used as a pull down circuit for a source line.

FIG. 9 depicts another design previously disclosed by Applicant where aplurality of dummy memory cells are used as a pull down circuit for asource line.

FIG. 10A depicts a prior art memory cell and erase gate strap cell.

FIG. 10B depicts a prior art memory cell and source line strap cell.

FIG. 10C depicts a prior art memory cell and control gate strap cell.

FIG. 10D depicts a prior art memory cell and word line strap cell.

FIG. 11A depicts a prior art memory array comprising an erase gatestrap.

FIG. 11B depicts a prior art memory array comprising a source linestrap.

FIG. 11C depicts a prior art memory array comprising a control gatestrap.

FIG. 11D depicts a prior art memory array comprising a word line strap.

FIG. 12 depicts an embodiment with a strap cell used as pull downcircuit for a source line.

FIG. 13 depicts a layout diagram of an embodiment of a memory arraycomprising an erase gate strap used in a source line pull down circuit.

FIG. 14 depicts a layout diagram of another embodiment of a memory arraycomprising an erase gate strap used in a source line pull down circuit.

FIG. 15 depicts a layout diagram of another embodiment of a memory arraycomprising an erase gate strap used in a source line pull down circuit.

FIG. 16 depicts a layout diagram of an embodiment of a memory arraycomprising a source line strap used in a source line pull down circuit.

FIG. 17 depicts a layout diagram of an embodiment of a memory arraycomprising a control gate strap used in a source line pull down circuit.

FIG. 18 depicts a layout diagram of an embodiment of a memory arraycomprising a word line strap used in a source line pull down circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 12 depicts an embodiment with a strap cell used as a pull downcircuit for a source line. Memory system 1200 comprises memory cell1010, which comprises the same components described previously formemory cell 1010 with respect to FIGS. 10A-10D, in particular memorycell 1010 comprises a first word line terminal 1012, a first controlgate terminal 1013, a first erase gate terminal 1014, a first sourceline terminal 1015 and a first bit line terminal 1011. Memory system1200 also comprises strap cell 1020, which can be any of strap cells1020-1, 1020-2, 1020-3, and 1020-4 described previously with respect toFIGS. 10A-10D and 11A-11D.

Unlike in the prior art, second bit line terminal 1021 of strap cell1020 is connected to pull down circuit contact 1201 (which can comprise,for example, a via between layers), which in turn connects outside ofthe memory array to pull down circuit 1210. Pull down circuit 1210comprises switch 1211 that, in response to a control signal, will beselectively connected to ground or a voltage source such as VDD.

When memory cell 1010 is in read mode or erase mode, first source lineterminal 1015 is coupled to source line 1105, which is coupled to strapcell 1020 and pull down circuit 1210 to ground. Thus, first source lineterminal 1015, source line 1105, and second source line terminal 1025will be pulled down to ground through strap cell 1020. Optionally, morethan one strap cell 1020 can be coupled to first source line terminal1015 to strengthen the pull down of the first source line terminal 1015and source line 1105 to ground so as to cause first source line terminal1015 and source line 1105 to pull to ground faster.

When the memory cell 1010 is in program mode, second bit line terminal1021 is coupled to an inhibit voltage source such as VDD through switch1211 in pull down circuit 1210. This will place strap cell 1020 in aprogram inhibit mode, which maintains strap cell 1020 in an erasedstate, even while memory cell 1010 is programmed.

Strap cell 1020 is produced in a neutral state, in which it conductscurrent (equivalent to an erased state). When memory cell 1010 iserased, strap cell 1020 similarly experiences erase potentials, and thusremains in the erased state at all times, or optionally is not erasedand is kept in a neutral state, in which current flows through strapcell 1020, since when memory cell 1010 is programmed, strap cell 1020experiences inhibit program potentials responsive to pull down circuit1210.

FIGS. 13-18 depict exemplary layouts of embodiments utilizing the fourtypes of strap cells (erase gate strap cell 1020-1, source line strapcell 1020-2, control gate strap cell 1020-3, and word line strap cell1020-4) for strap cell 1020, respectively.

FIG. 13 depicts array 1300, which is similar to array 1100-1, exceptthat the bit line terminal 1021 (not shown, but seen in FIG. 10A-10D) inerase gate strap 1310 is connected to pull down circuit contacts 1201 onboth ends of the bit line, which in turn connects to a switchablecontact of respective pull down circuits 1210 (not shown here, but shownin FIG. 12). Cell 1010 and erase gate strap cell 1020-1 share sourceline 1105, and source line 1105 is pulled down to ground through pulldown circuit contacts 1201 and respective pull down circuits 1210 duringa read mode or an erase mode, and is pulled to VDD through pull downcircuit contacts 1201 responsive to pull down circuits 1210 during aprogram mode, as discussed previously with reference to FIG. 12.

FIG. 14 depicts array 1400, which is similar to array 1300, except thaterase gate strap 1410 is wider than erase gate strap 1310, and erasegate strap cell 1020-2 is wider in array 1400 than in array 1300, inthis example, by a factor of 2×. This increases the pull downcapability. Cell 1010 and erase gate strap cell 1020-2 share source line1105, and source line 1105 is pulled down to ground through pull downcircuit contacts 1201 responsive to pull down circuits 1210 during aread mode or an erase mode, and is pulled to VDD through pull downcircuit contacts 1201 responsive to pull down circuits 1210 during aprogram mode, as discussed previously with reference to FIG. 12.

FIG. 15 depicts array 1500, which is similar to array 1400 of FIG. 14,except that (1) erase gate strap 1410 has been replaced with erase gatestrap 1510, which comprises two columns of erase gate strap cells, eachsimilar in size to a column of memory cells, (2) there are two erasegate strap cells 1020-2 instead of one, and (3) erase gate strap 1510has four pull down circuit contacts 1201 each connected to a respectivebit line terminal, instead of two. Array 1500 might be easier tomanufacture than array 1400 due to the relative uniformity among thecolumns of normal cells and the two columns of erase gate strap cells.

FIG. 16 depicts array 1600, which comprises source line strap 1610.Array 1600 is similar to array 1100-2 of FIG. 11B, except that he bitline terminal in source line strap 1610 is connected to pull downcircuit contacts 1201 on both ends of the bit line, which in turnconnects to a switchable contact of respective pull down circuits 1210(not shown here, but shown in FIG. 12). Cell 1010 and source line strapcell 1020-2 share source line 1105, and shared source line 1105 ispulled down to ground through pull down circuit contact 1201 responsiveto pull down circuits 1210 during a read or erase mode, and is pulled toVDD through pull down circuit contacts 1201 responsive to pull downcircuits 1210 during a program mode, as discussed previously withreference to FIG. 12.

FIG. 17 depicts array 1700, which comprises control gate line strap1710. Array 1700 is similar to array 1100-3 of FIG. 11C, except that thebit line terminal in control gate line strap 1710 is connected to pulldown circuit contacts 1201 on both ends of the bit line, which in turnconnect to switchable contacts of respective pull down circuits 1210(not shown here, but shown in FIG. 12). Cell 1010 and control gate strapcell 1020-3 share source line 1105, and source line 1105 is pulled downto ground through pull down circuit contacts 1201 responsive to pulldown circuit 1210 during a read mode or erase mode, and is pulled to VDDthrough pull down circuit contacts 1201 responsive to pull down circuits1210 during a program mode, as discussed previously with reference toFIG. 12.

FIG. 18 depicts array 1800, which comprises word line strap 1810. Array1800 is similar to array 1100-4 of FIG. 11D, except that the bit lineterminals in word line strap 1810 are respectively connected to pulldown circuit contacts 1201 on both ends of the bit line, which in turnconnects to the switchable contacts of respective pull down circuits1210 (not shown here, but shown in FIG. 12). Cell 1010 and word linestrap cell 1020-4 share source line 1105, and source line 1105 is pulleddown to ground through pull down circuit contacts 1201 responsive topull down circuits 1210 during a read mode or erase mode, and is pulledto VDD through pull down circuit contacts 1201 responsive to pull downcircuits 1210 during a program mode, as discussed previously withreference to FIG. 12.

The embodiments described above utilize less die space than the systemof the prior art systems of FIGS. 8 and 9. This is a significantimprovement that will reduce manufacturing complexity and cost.

It should be noted that, as used herein, the terms “over” and “on” bothinclusively include “directly on” (no intermediate materials, elementsor space disposed therebetween) and “indirectly on” (intermediatematerials, elements or space disposed therebetween). Likewise, the term“adjacent” includes “directly adjacent” (no intermediate materials,elements or space disposed therebetween) and “indirectly adjacent”(intermediate materials, elements or space disposed there between), and“coupled” includes “directly coupled to” (no intermediate materials orelements therebetween that electrically connect the elements together)and “indirectly coupled to” (intermediate materials or elementstherebetween that electrically connect the elements together). Forexample, forming an element “over a substrate” can include forming theelement directly on the substrate with no intermediatematerials/elements therebetween, as well as forming the elementindirectly on the substrate with one or more intermediatematerials/elements there between.

What is claimed is:
 1. A memory system comprising: a memory cellcomprising a first bit line terminal and a first source line terminal; astrap cell comprising a second bit line terminal and a second sourceline terminal; a source line coupled to the first source line terminaland the second source line terminal; and a pull down circuit thatselectively couples the second bitline terminal to ground when thememory cell is being read or erased and to a voltage source when thememory cell is being programmed.
 2. The system of claim 1, wherein thememory cell comprises a first word line terminal and the strap cellcomprises a second word line terminal.
 3. The system of claim 2, whereinthe memory cell comprises a first control gate terminal and the strapcell comprises a second control gate terminal.
 4. The system of claim 3,wherein the memory cell comprises a first erase gate terminal and thestrap cell comprises a second erase gate terminal.
 5. The system ofclaim 4, wherein the strap cell is a source line strap cell, wherein thesecond source line terminal is connected to a source line contact. 6.The system of claim 4, wherein the strap cell is a word line strap cell,wherein the second word line terminal is connected to a word linecontact.
 7. The system of claim 4, wherein the strap cell is a controlgate strap cell, wherein the second control line terminal is connectedto a control gate contact.
 8. The system of claim 4, wherein the strapcell is an erase gate strap cell wherein the second erase gate terminalis connected to an erase gate contact.
 9. The system of claim 3, whereinthe strap cell is a source line strap cell, wherein the second sourceline terminal is connected to a source line contact.
 10. The system ofclaim 3, wherein the strap cell is a word line strap cell, wherein thesecond word line terminal is connected to a word line contact.
 11. Thesystem of claim 3, wherein the strap cell is a control gate strap cell,wherein the second control line terminal is connected to a control gatecontact.
 13. The system of claim 2, wherein the strap cell is a sourceline strap cell, wherein the second source line terminal is connected toa source line contact.
 14. The system of claim 2, wherein the strap cellis a word line strap cell, wherein the second word line terminal isconnected to a word line contact.
 15. The system of claim 1, wherein thestrap cell is a source line strap cell, wherein the second source lineterminal is connected to a source line contact.